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Analog Electronic Circuits

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Phase Locked Loops & VCO

Question
10 out of 12
 

A PLL has free running frequency of 500kHz and bandwidth of the low pass filter is 10kHz. Will the loop acquire lock for an input signal of 600kHz? Justify the answer. Assume that the phase detector produces sum and difference frequency components.

 

The phase detector output is
fs+fo = 600 kHz + 500 kHz = 1100 kHz
fs-fo 600 kHz - 500 kHz = 1100 kHz

The phase detector output is Since both the frequency components are outside the pass band of low pass filter, the PLL will not acquire lock.