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Flip Flops

  • It is an electronic circuit that has two stable states & can be used to store state information. It is basically a bistable multivibrator or latch or toggle.
  1. S-R (Set-Reset) Flip-flops

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Fig. : Block diagram Fig. : NOR based S-R flip-flop
 

Table

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  1. Clocked S-R Flip-flop
    The clocked SR flip-flop shown in fig. 8 (d) consists of a basic NOR flip-flop and two AND gates.

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Fig. : Clocked S-R Flip-flop

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Table S-R Flip-flop Truth Table

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The disadvantage of S-R flip-flop is for S = 1, R = 1 output cannot be determined. This can be eliminated in J-K flip-flop.

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Fig. : Graphic symbol of J-K flip flop

  1. J-K Flip-flops :
    The Master-Slave JK Flip-flop
    The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. The outputs from Q and 750.png from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip-flop being connected to the two inputs of the “Slave” flip-flop. This feedback configuration from the slave’s output to the master’s input gives the characteristic toggle of the JK flip-flop as shown in fig.

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Fig. : The Master-Slave JK Flip-Flop
 

Master-Slave JK Flip-flop is a “Synchronous” device as it only passes data with the timing of the clock signal.

  1. D Flip-flops :
    It has only one input known as D (Delay) & two outputs Q & 760.png.

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Fig. : D-flip-flop Using NAND gates
 

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Fig. : Logic symbol
 

Table

 

  1. T Flip-flops
    It is also known as trigger or toggle flip flop.

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Fig. : Block diagram of T flip flop

Table

 





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