Coupon Accepted Successfully!


Pin Diagram of 8259A

Pin diagram of 8259
VCC 5-V supply
GND Ground
CS (Chip Select) When the chip select pin is active low, this pin enables RD and WR operation between the CPU and the 8259A. INTA functions are independent of CS.
WR (Write) A low on this pin, when CS is low, enables the 8259A for write operation. This pin also enables to accept command words from the CPU.
RD (Read) When RD is active low and CS is low, this pin enables the 8259A to release status onto the data bus for the CPU.
D7 – D0 (I/O Bi-directional Data Bus) These pins are used as bi-directional data bus. The control, status and interrupt-vector informations are transferred through this bus.
CAS0 – CAS2 (I/O Cascade Lines) A 8279A has only eight interrupts. When number of interrupts requirement is more, multiple interrupt controller must be connected in cascade. The CAS lines of a 8259A bus is used to control a multiple 8259A structure. These pins are outputs for a master 8259A and inputs for a slave 8259A.
SP / EN (I/O Slave Program/Enable Buffer) This is a dual function pin. When this IC is used in the buffered mode, it can be used as an output to control buffer transceivers (EN). If this IC is not in the buffered mode, it is used as an input to designate a master (SP = 1) or slave (SP = 0).
INT (Interrupt) This pin goes high whenever a valid interrupt request is asserted. This pin signal is used to interrupt the CPU. Therefore it is connected to the CPU’s interrupt pin.
IR0 – IR7 (Interrupt Requests) These pins are used as asynchronous inputs. Each pin can be used to receive an interrupt request to the CPU by raising an IR input from low to high. The interrupt pin must be maintained high level until this is acknowledged (edge-triggered mode), or just by a high level on an IR input (level triggered mode).
INTA (Interrupt Acknowledge) This pin becomes high when a valid interrupt request is asserted. This pin is used to enable 8259A interrupt-vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the CPU.
A0 (Address Line) This pin works in conjunction with the CSWR, and RD pins. This is also used by the 8259A to read various command words the CPU writes and the status the CPU wishes to read. Generally, this is connected to the CPU A0 address line.

Test Your Skills Now!
Take a Quiz now
Reviewer Name