Architecture Of 8086
Table: Comparison between 8085 and 8086 microprocessors
|8085 Microprocessor||8086 Microprocessor|
|8085 is an 8-bit processor created in 1977 and it has 8-bit data bus||8086 is a 16-bit processor developed in 1978 and it has a 16-bit data bus.|
|8085 is manufactured using NMOS technology and this processor IC consists of about 6200 transistors.||8086 is fabricated based on HMOS technology and this processor IC consists of approximately 29000 transistors.|
|8085 has a 16-bit address bus and is able to access 216 = 64 KB memory locations.||8086 has a 20-bit address bus and is able to access 220 =1 MB memory locations.|
|Number of flags are 5.||Number of flags are 9.|
|Pipelining concept is not used in 8085.||8086 uses pipelining.|
|Instruction queue does not exist in 8085 and sequentially execute instructions.||8086 has a 6-byte instruction queue in BIU.|
|No segment registers exist in 8085.||There are four segment registers, CS, DE, ES, SS in 8086.|
|Only four types of addressing modes are available.||Eight types of addressing modes are available.|
|8085 has less instruction than 8086. Direct multiplication, divide, string-byte block movement and loop instructions are not available in 8085.||8086 has more instructions than 8085. Direct multiplication, divide, string-byte block movement and loop instructions are available in 8085.|
Table: Comparison between 8086 and 8088
|8086 Microprocessor||8088 Microprocessor|
|8086 is a 16-bit processor developed in 1978 and it has a 16-bit data bus.||8088 is an 8-bit processor developed in 1979 and it has 8-bit data bus.|
|8086 has a 6-byte instruction queue in BIU.||8086 has a 4-byte instruction queue in BIU.|
|The 8086 BIU fills the queue when its queue has an empty space of 2 bytes.||The 8088 BIU fetches a new instruction byte to load into the queue, whenever there is one byte hole in the queue.|
|As 8086 has a 16-bit data bus, 8-bit or 16-bit memory read/write operation is possible in a single operation.||As 8088 has an 8-bit data bus, it can read 8 bits data from memory or I/O devices and write 8-bits of data to memory or I/O devices. To read 16-bit data, the 8088 requires two memory read operations.|
|AD15âAD8 pins are used as time multiplexed address/ data bus in 8086.||AD7âAD0 pins are used as time multiplexed address/data bus and A15âA pins are used as address bus only in 8088.|
|BHE is present in 8086 and the external memory interfaces have even or odd address banks.||BHE is not present in 8088. Therefore, the external memory interfaced will not have been even or odd address banks. The external memory will therefore be byte oriented as 8085|
|In 8086 I/O and memory pin is represented as IO/M.||In 8088 I/O and memory pin has been inverted and represented as IO/M.|
|The status signals of 8086 are S2, S1 and S0.||The status signals of 8086 are IO/M, DT/R and SS0.|
|The overall execution time of the instructions in 8086 is less compared to 8088 as 8086 has 16-bit data bus and only 4 clock cycles are required to execute.||The overall execution time of the instructions in 8088 is more due to the 8-bit data bus and the 16-bit operations require additional 4 clock cycles.|
Block diagram of 8086 microprocessor
Fetch and Execute
The fetch and execute operations of 8086 are given below:
- The BIU output is the content of the Instruction Pointer register (IP), which is put on the address bus. Therefore, a byte or word can be read from a specified address into the BIU.
- The content of the instruction pointer register is incremented by 1 to get ready for the next instruction fetch.
- After receiving the opcode and operand of instruction, the instruction code must be passed to the queue which is a FIFO (first-in first-out) register.
- Initially, the queue is empty. As soon as the BIU puts the instruction on the queue, the EU draws the instruction from the queue and starts execution.
- While the EU is executing one instruction, the BIU will continue to fetch new instructions. Depending upon the execution time of the instruction, the BIU can fill the queue with instructions. When execution time is more, the queue will be filled completely before the EU is ready to get the next instruction for execution. Figure 9.2(b) shows the pipeline concept of fetch and execution in BIU and EU. In this architecture, BIU and EU are operating independently. The advantage of this architecture is that the EU executes instructions continuously without waiting of fetching the instruction in BIU.
General instruction fetch and execution for conventional processors (8085)
Instruction fetch and execution of the 8086 processor