Maskable/Vectored Interrupts of 8085
Maskable interrupts and vector locations
Masking RST 5.5, RST 6.5 and RST 7.5
Step-1 The interrupt process must be enabled using the EI instruction.
Step-2 The 8085 should check for an interrupt during the execution of every instruction.
Step-3 When there is an interrupt and the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and then reset the interrupt flip flop.
Step-4 Thereafter, the microprocessor executes the CALL instruction which sends the execution to the appropriate memory location according to the interrupt vector table.
Step-5 When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack.
Step-6 The microprocessor jumps to the specific service routine. The Interrupt Service Routine (ISR) must incorporate the instruction EI to re-enable the interrupt process.
Step-7 At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.
The 8085 non-vectored interrupt processes are completed by the following steps:
Step-1 The interrupt process should be enabled using the EI instruction.
Step-2 The 8085 checks for an interrupt during the execution of every instruction.
Step-3 If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted.
Step-4 INTA allows the I/O device to send an RST instruction through data bus.
Step-5 After receiving the INTA signal, the microprocessor saves the memory location of the next instruction on the stack and the program is transferred to βcallβ location (ISR Call) specified by the RST instruction.
Step-6 The microprocessor performs the ISR. ISR must include the βEIβ instruction to enable further interrupt within the program.
Step-7 RET instruction at the end of the ISR allows the microprocessor to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.
Table 8085 interrupts
|Interrupt||Maskable||Masking method||Vectored||Memory||Triggering method|
|RST 5.5||Yes||DI/EI SIM||Yes||No||Level sensitive|
|RST 6.5||Yes||DI/EI SIM||Yes||No||Level sensitive|
|RST 7.5||Yes||DI/EI SIM||Yes||Yes||Edge sensitive|
|TRAP||No||None||Yes||No||Level and edge sensitive|