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The 8085 Interrupts

When a device interrrupts, it actually wants the microprocessor to give a service, which is equivalent to asking the microprocessor to call a subroutine. 

INTR is a maskable interrupt. When the interrupt occurs, the processor fetches from the bus one instruction, usually one od EI and DI instructions. 

Table: RST n inturrupts vector address
 
Restart instruction Hex Code Equivalent Vector Address
RST0 C7 CALL 0000H
RST1 CF CALL 0008H
RST2 D7 CALL 0010H
RST3 DF CALL 0018H
RST4 E7 CALL 0020H
RST5 EF CALL 0028H
RST6 F7 CALL 0030H
RST7 FF CALL 0038H
 
RST 5.5 is a maskable interrupt. When this interrupt is received, the processor saves the contents of the program counter register into the stack and the branches to 002CH address. 
 
RST 6.5 is a maskable interrupt. When this interrupt is received, the processor saves the contents of the program counter register into the stack and branches to 0034H address. 
 
RST 7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the program counter register into the stack and branches to 003CH address. 
 
TRAP is a non-maskable interrupt. It does not need to be enabled, as it cannot be disabled. It has the highest priority amongst all interrupts. This is edge and level sensitive. This TRAP signal needs to be high and stay high for recognisation. Once it is recognised, it does not need to be recognised again until it becomes low and then high again.
 
Table: 8085 interrupts
 
Interrupt Maskable Vectored
INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

 

8085 microprocessor interrupts




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