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Interrupt Sequence

The interrupt sequence for an interrupt in the 8085-microprocessor system has been explained below:

  • One or more of the INTERRUPT REQUEST lines (IR7 to IR0) are raised high, setting the corresponding IRR bits.
  • The 8259A evaluates these requests, and sends an INT to the CPU.
  • The CPU acknowledges the INT and responds with an INTA pulse.
  • After receiving an INTA from the CPU group, the highest priority ISR bit is set, and the corresponding IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit data bus through its D7 to D0 pins.
  • This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group.
  • These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the higher 8-bit address is released at the second INTA pulse.
  • This completes the 3-byte CALL instruction released by the 8259A. In the AEOI (Automatic End Of Interrupt) mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI (End Of Interrupt) command is issued at the end of the interrupt sequence.

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